In the integrated circuit industry today, millions of semiconductor transistors are built on a single chip. As CMOS transistors, also referred to as MOSFETs, are scaled down in size, one of the most important challenges facing a device designer are short channel effects (SCE) in reduced gate length devices. It is well-known that short channel effects of MOSFET devices include VT roll-off, drain induced barrier lowering (DIBL), subthreshold swing degradation, gate-to-drain overlap capacitance and gate-induced-drain-leakage (GIDL) current. Short channel effects (SCE) are a function of several processing parameters including width and depth of S/D regions and S/D region dopant concentration profiles. For example, since SCE is related to the junction depth (xj), shallower S/D junction depths with lighter doping can improve transistor operating characteristics.
The formation of contact holes to form electrical connections to source/drain regions and/or gate electrodes in a typical CMOS process flow include depositing nitride contact etch stop layers over the process surface after the formation of silicided source/drain regions and/or gate electrodes. A pre-metal dielectric (PMD) layer is then deposited and followed by formation of a contact hole to the source/drain regions and/or gate electrodes by masking and dry etching process steps.
One problem in the prior art process is unintentional yet difficult to avoid removal of underlying critical material layers during dry etching process step in a uniform manner, such as silicide regions and (shallow trench isolation (STI) oxide regions, for example at the STI edge. As a result, the formation of shallow source/drain junctions is increasingly problematical due to the difficulty in controlling overetch phenomenon in nitride etch stop layers. For example overetching underlying silicide and STI oxide regions leads to increased junction leakage and even shorts to substrate, thereby compromising device reliability, performance and yield. Moreover, conventional nitride material formation processes have been found to contribute to the presence of hydrogen which can form charge carrier traps in nearby gate dielectric by diffusive transport leading to degraded reliability and performance including hot carrier induced degradation, Fowler-Nordheim tunneling.
These and other shortcomings demonstrate a need in the MOSFET integrated circuit manufacturing art for improved contact etch stop layers and methods for forming the same including contact hole formation to improve CMOS device performance, reliability, and yield.
It is therefore an object of the present invention to provide improved contact etch stop layers and methods for forming the same including contact hole formation to improve CMOS device performance, reliability, and yield, in addition to overcoming other shortcomings of the prior art.